Edward Ding
University of California, Santa Barbara
Electrical & Computer Engineering, BS/MS Combined Degree (2022-2027)
eding2019@gmail.com
Half-Adder Test Chip Fabrication
- Designed and fabricated working half-adder ASIC test chip from scratch in the UCSB Teaching Cleanroom.
- Overcame process limitations by leveraging NMOS-only logic with resistive pull-up network.
- Performed physical design (PD) and design verification (DV) using Siemens L-Edit and created customized mask set.
- Performed various fabrication steps, including patterning, metrology, doping (thermal diffusion), etching (BHF), gate oxide growth (wet/dry oxidation), electrical testing, etc.
- Analyzed electrical performance using semiconductor testbench to fine-tune chip fabrication process and improve yield.
Programmable FIR Filter Core
- Designed a functional 300 MHz 24-bit Programmable Finite Impulse Response (FIR) chip in Cadence Virtuoso.
- Performed circuit design with custom 8-bit array multiplier logic on the Skywater 130nm PDK.
- Leverage hierarchical design practices to manage project complexity (50K+ total transistor count).
- Achieved over 10 million samples per second at less than 90 mW power consumption.
- Performed pre-silicon verification and power analysis using Virtuoso ADE Suite.